1. Field of the Invention
This invention relates generally to masking techniques for semiconductor fabrication, and more particularly to masking techniques for forming contact imprint lithography reticles.
2. Description of the Related Art
As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being reduced in size. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are also constantly being decreased to facilitate this size reduction. Additionally, the spacing between features (e.g., DRAM capacitors) is also being decreased in size to offer a higher density of features.
The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. DRAM memory cells typically include two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. By decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices. Other examples of integrated circuit memories include MRAM (including magneto resistive elements), programmable fuse memories, programmable conductor memories (including metal-doped chalcogenide glass elements), SRAM, SDRAM, EEPROM and other volatile and non-volatile memory schemes.
Lithography, such as photolithography, is commonly used to pattern features, such as conductive lines. However, due to factors such as optics and the wavelength of light (or electromagnetic radiation) used to pattern features, lithographic techniques each have a lower limit below which a particular technique cannot reliably form features. The lower limit for photolithography is currently between about 30-50 nm.
High resolution processes, such as electron beam (“e-beam”) lithography, are typically employed for defining the desired patterns in lithography reticles which can then be repeatedly employed in applying those patterns to substrates (e.g., wafers) in which integrated circuits will be formed. The reticles can be used for photolithography or contact imprint lithography. The lower limit of electron beam lithography is about 10 nm or less, though equipment capable of achieving this limit is expensive. Consequently, the lower limit of a lithographic technique is an impediment to further reduction in feature sizes.